Kontron COMe-cDC2 Manuale Utente Pagina 69
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COMe-cDC2 / BIOS Operation
SuperIO Configuration
Feature Option Description
Onboard Floppy Controller
Disabled
Enabled
Enables / Disables the floppy controller in BIOS
Serial Port1 Address Disabled
3F8/IRQ4
2F8/IRQ3
3E8/IRQ4
2E8/IRQ3
Selects the Address of COM Port 1
Serial Port2 Address Disabled
3F8/IRQ4
2F8/IRQ3
3E8/IRQ4
2E8/IRQ3
Selects the Address of COM Port 2
Serial Port2 Mode
Normal
IrDA
ASK IR
Parallel Port Address Disabled
378
278
3BC
Selects the Address of the LPT Port
Parallel Port Mode
Normal
Bi-Directional
ECP
EPP+SPP
ECP+EPP
Allows BIOS to Select Parallel Port Mode. (Only visible
when Parallel Port enabled.)
Parallel Port IRQ IRQ5
IRQ7
Allows BIOS to Select Parallel Port IRQ. (Only visible
when Parallel Port enabled.)
69
- COMe-cDC2 1
- » Table of Contents « 3
- 1 User Information 6
- 1.5 Warranty 7
- 1.6 Technical Support 7
- 2 Introduction 8
- 2.5 COM Express® Benefits 9
- 3 Product Specification 10
- Accessories 11
- 3.2 Functional Specification 12
- Connectivity 13
- Misc Interfaces and Features 14
- Kontron Features 14
- Power Features 14
- Supported Operating Systems 14
- 3.3 Block Diagram 15
- 3.4 Electrical Specification 16
- 3.4.5 ATX Mode 17
- 3.4.6 Single Supply Mode 17
- 3.5 Power Control 18
- 3.6.2 Humidity 19
- CE marking 20
- WEEE Directive 20
- Conformal Coating 20
- Shock & Vibration 21
- 3.8 MTBF 22
- 3.9 Mechanical Specification 23
- 3.10 Thermal Management 24
- 3.11 Heatspreader 24
- 3.12 Onboard Fan Connector 25
- 4 Features and Interfaces 27
- 4.2 S5 Eco Mode 28
- 4.4 LPC boot 30
- 4.5 M.A.R.S 31
- 4.6 Fast I2C 32
- 4.7 JIDA16 and JIDA32 33
- 4.8 K-Station 1 34
- 4.9.1 I2C 35
- 4.9.2 Storage 35
- 4.9.3 GPIO 35
- 4.9.4 Hardware Monitor 35
- 4.10.1 I2C 35
- 4.10.2 Storage 36
- 4.10.3 GPIO 36
- 4.10.5 SIO Winbond 83627DHGP 36
- 4.10.6 SIO Winbond 83627HG 37
- Configuration 38
- Time-out events 39
- WDT Signal 39
- 4.13 Flash Backup Feature 40
- 4.14 Speedstep Technology 42
- 4.15 C-States 43
- 4.16 Hyper Threading 44
- 5 System Ressources 46
- 5.3 Memory Area 47
- 5.4 I/O Address Map 48
- 5.7 JILI I2C Bus 48
- 6 Connectors 49
- 6.2 Pinout List 50
- 6.2.2 Connector X1A Row A 51
- COMe-cDC2 / Connectors 52
- 6.2.3 Connector X1A Row B 53
- 6.2.4 Connector X1B Row C 55
- 6.2.5 Connector X1B Row D 57
- 7 BIOS Operation 59
- 7.3 Setup Guide 60
- 7.4 BIOS Setup 62
- 7.4.2 Module Info 63
- Module Software Revisions 64
- Current LVDS Configuration 64
- 7.4.3 Advanced Menu 65
- CPU Configuration 66
- IDE Configuration 67
- IDE Device Submenu 68
- SuperIO Configuration 69
- ACPI Settings 70
- ACPI Cooling Options 71
- PCI Express Configuration 73
- USB Configuration 74
- COMe-cDC2 / BIOS Operation 75
- Hardware Health 76
- Module Hardware Health 77
- Baseboard Hardware Health 78
- Miscellaneous Settings 79
- MARS Interface Configuration 80
- Watchdog 81
- Remote Access Configuration 82
- LAN Controller 83
- GPIO Level Configuration 84
- Trusted Computing 85
- 7.4.4 PCIPnP Menu 86
- 7.4.5 Boot 87
- Boot Setting Configuration 88
- 7.4.6 Security 89
- 7.4.7 Chipset 90
- North Bridge Configuration 91
- Display Control 92
- Internal LVDS Configuration 93
- Southbridge Configuration 94
- LPC Decode Range 95
- 7.4.8 Exit Menu 96
- Corporate Offices 97
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